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RT9611A/b ? ds9611a/b-03 june 2012 www.richtek.com 1 ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. synchronous rectified buck mosfet drivers features z drive two n-mosfets z adaptive shoot through protection z embedded bootstrap diode z support high switching frequency z fast output rise time z tri-state input for bridge shutdown z disable control input z small sop-8, sop-8 (exposed pad) and 8-lead wdfn packages z rohs compliant and halogen free ordering information applications z z z z z core voltage supplies for desktop, motherboard cpu z z z z z high frequency low profile dc/dc converters z z z z z high current low voltage dc/dc converters note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. general description the RT9611A/b is a high frequency, synchronous rectified, single phase dual mosfet driver designed to adapt from normal mosfet driving applications to high performance cpu vr driving capabilities. the RT9611A/b can be utilized under both v cc = 5v or v cc = 12v applications. the RT9611A/b also builds in an internal power switch to replace external boot strap diode. the RT9611A/b can support switching frequency efficiently up to 500khz. the RT9611A/b has the ugate driving circuit and the lgate driving circuit for synchronous rectified dc/dc converter applications. the driving rise/ fall time capability is designed within 30ns and the shoot through protection mechanism is designed to prevent shoot through of high side and low side power mosfets. the RT9611A/b has pwm tri-state shut down and od input shut down functions which can force driver output into high impedance. the difference of the RT9611A and the rt9611b is the propagation delay, t ugatepdh . the rt9611b has comparatively large t ugatepdh than rt9611b. hence, the RT9611A is usually recommended to be utilized in performance oriented applications, such as high power density cpu vr or gpu vr. the RT9611A/b comes in a small footprint with 8-pin packages. the choice of packages type includes sop-8, sop-8 (exposed pad) and wdfn-8el 3x3. lead plating system g : green (halogen free and pb free) z : eco (ecological element with halogen free and pb free) RT9611A/b package type s : sop-8 sp : sop-8 (exposed pad-option1) qw : wdfn-8el 3x3 (w-type) long dead time short dead time
RT9611A/b 2 ds9611a/b-03 june 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. marking information rt9611xgs : product number x : a or b ymdnn : date code rt9611xzs : product number x : a or b ymdnn : date code 02=ym dnn 02= : product code ymdnn : date code 04=ym dnn 04= : product code ymdnn : date code rt9611xgsp : product number x : a or b ymdnn : date code rt9611xzsp : product number x : a or b ymdnn : date code rt9611xgs rt9611xzs RT9611Agqw rt9611xgsp rt9611bgqw rt9611xzsp pin configurations (top view) 2 3 4 5 8 7 6 boot vcc pwm ugate lgate gnd phase od boot vcc pwm od 7 6 5 1 2 3 4 8 gnd 9 ugate lgate gnd phase boot pwm vcc ugate phase lgate gnd gnd 2 3 4 5 6 7 8 9 od sop-8 (exposed pad) wdfn-8el 3x3 sop-8 rt9611x gsymdnn rt9611x zsymdnn rt9611x gspymdnn rt9611x zspymdnn 02 : product code ymdnn : date code 04 : product code ymdnn : date code RT9611Azqw r t9611bzqw 02 ym dnn 04 ym dnn
RT9611A/b 3 ds9611a/b-03 june 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical application circuit timing diagram pwm ugate lgate t pdhugate t pdllgate t pdlugate t pdhlgate 90% 90% 1.5v 1.5v 1.5v 1.5v vcc pwm gnd boot ugate phase lgate RT9611A/b q1 atx_12v pwm + atx_12v v core q2 1 2 8 5 7 6 4 3 c1 c2 c3 c4 c6 r1 r2 r3 r4 r5 l1 v in 5v od 10 1f 1 1f 2.2 0 1h 2.2 3.3nf 2200f x 2 c5 10f x 2 1000f x 3 c7 10f x 4
RT9611A/b 4 ds9611a/b-03 june 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. function block diagram pin no. sop-8 sop-8 (exposed pad) / wdfn-8el 3x3 pin name pin function 1 1 boot floating bootstrap supply pin for upper gate driver. 2 2 pwm input pwm signal for controlling the driver. 3 3 od output disable. when low, both ugate and lgate are driven low and the normal operation is disabled. 4 4 vcc 12v supply voltage. 5 5 lgate lower gate driver output. connected to gate of low side power n-mosfet. 6 6, 9 (exposed pad) gnd ground. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. 7 7 phase connect this pin to the source of the high side mosfet and the drain of the low side mosfet. 8 8 ugate upper gate driver output. connected this pin to gate of high side power n-mosfet. functional pin description shoot-through protection turn off detection shoot through protection input disable vcc pwm internal 3.6v boot ugate phase lgate gnd 15k 15k vcc por od bootstrap control 12k 12k 12k
RT9611A/b 5 ds9611a/b-03 june 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. absolute maximum ratings (note 1) z supply voltage, vcc ---------------------------------------------------------------------------------- ? 0.3v to 15v z boot to phase --------------------------------------------------------------------------------------- ? 0.3v to 15v z phase to gnd dc ---------------------------------------------------------------------------------------------------------- ? 5v to 15v < 200ns --------------------------------------------------------------------------------------------------- ? 10v to 30v z lgate dc ---------------------------------------------------------------------------------------------------------- (gnd ? 0.3v) to (v cc + 0.3v) < 200ns --------------------------------------------------------------------------------------------------- ? 2v to (v cc + 0.3v) z ugate ---------------------------------------------------------------------------------------------------- (v phase ? 0.3v) to (v boot + 0.3v) < 200ns --------------------------------------------------------------------------------------------------- (v phase ? 2v) to (v boot + 0.3v) z pwm input voltage ------------------------------------------------------------------------------------ (gnd ? 0.3v) to 7v z od ---------------------------------------------------------------------------------------------------------- (gnd ? 0.3v) to 7v z power dissipation, p d @ t a = 25 c sop-8 ----------------------------------------------------------------------------------------------------- 0.833w sop-8 (exposed pad) -------------------------------------------------------------------------------- 1.333w wdfn-8el 3x3 ----------------------------------------------------------------------------------------- 1.429w z package thermal resistance (note 2) sop-8, ja ----------------------------------------------------------------------------------------------- 120 c/w sop-8 (exposed pad), ja --------------------------------------------------------------------------- 75 c/w sop-8 (exposed pad), jc -------------------------------------------------------------------------- 15 c/w wdfn-8el 3x3, ja ------------------------------------------------------------------------------------ 70 c/w wdfn-8el 3x3, jc ----------------------------------------------------------------------------------- 8.2 c/w z lead temperature (soldering, 10 sec.) ------------------------------------------------------------ 260 c z junction temperature ---------------------------------------------------------------------------------- 150 c z storage temperature range ------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body model) --------------------------------------------------------------------------- 2kv recommended operating conditions (note 4) z supply voltage, vcc ---------------------------------------------------------------------------------- 12v 10% z junction temperature range ------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range ------------------------------------------------------------------------- ? 40 c to 85 c
RT9611A/b 6 ds9611a/b-03 june 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. parameter symbol test conditions min typ max unit power supply voltage v cc 4.5 -- 13.5 v power supply current i vcc v boot = 12v, pwm = 0v -- 1.2 -- ma power on reset por threshold v por v cc rising 3 4 4.4 v hysteresis v cc_hys -- 0.5 -- v pwm input maximum input current i pwm pwm = 0v or 5v -- 300 -- a pwm floating voltage v pwm_fl v cc = 12v 1.6 1.8 2 v pwm rising threshold v pwm_rth 2.8 -- -- v pwm falling threshold v pwm_fth -- -- 0.8 v output disable input od rising threshold v od_rth 1 1.3 1.6 v od hysteresis v od_hys -- 0.3 -- v timing ugate rise time t ugater v cc = 12v, 3nf load -- 25 -- ns ugate fall time t ugatef v cc = 12v, 3nf load -- 12 -- ns lgate rise time t lgater v cc = 12v, 3nf load -- 24 -- ns lgate fall time t lgatef v cc = 12v, 3nf load -- 10 -- ns RT9611A -- 22 -- rt9611b t ugatepdh -- 60 -- t ugatepdl v boot ? v phase = 12v see timing diagram -- 22 -- t lgatepdh -- 20 -- propagation delay RT9611A/b t lgatepdl see timing diagram -- 8 -- ns output ugate drive source i ugatesr v boot ? v phase = 12v v ugate ? v ph as e = 12v -- 2 -- a ugate drive sink r ugatesk v boot ? v phase = 12v -- 1.4 -- lgate drive source i lgatesr v cc = 12v, v lgate = 2v -- 2.2 -- a lgate drive sink r lgatesk v cc = 12v -- 1.1 -- note 1. stresses beyond those listed ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions may affect device reliability. note 2. ja is measured at t a = 25 c on a high effective thermal conductivity four-layer test board per jedec 51-7. jc is measured at the exposed pad of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. electrical characteristics (v cc = 12v, t a = 25 c, unless otherwise specified)
RT9611A/b 7 ds9611a/b-03 june 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical operating characteristics pwm rising edge time (20ns/div) ugate (20v/div) phase (10v/div) lgate (10v/div) pwm (5v/div) v in = 12v, no load pwm falling edge time (20ns/div) ugate (20v/div) phase (10v/div) lgate (10v/div) pwm (5v/div) v in = 12v, no load drive enable time (1 s/div) v in = 12v, no load ugate (20v/div) phase (10v/div) lgate (10v/div) od (5v/div) drive disable time (1 s/div) ugate (20v/div) phase (10v/div) lgate (10v/div) od (5v/div) v in = 12v, no load time (20ns/div) dead time (5v/div) v in = 12v, pwm rising, no load lgate phase ugate dead time time (20ns/div) lgate phase ugate (5v/div) v in = 12v, pwm falling, no load
RT9611A/b 8 ds9611a/b-03 june 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. dead time time (20ns/div) (5v/div) lgate phase ugate v in = 12v, pwm rising, full load dead time time (20ns/div) lgate phase ugate (5v/div) v in = 12v, pwm falling, full load short pulse time (20ns/div) (5v/div) lgate phase ugate v in = 12v, start up
RT9611A/b 9 ds9611a/b-03 june 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. propagation delay, t ugatepdh . the rt9611b has comparatively large t ugatepdh to further prevent from shoot through when high side power mosfets are going to be turned on. the long propagation delay of the rt9611b sacrifices efficiency for compromise of system safety. hence, the RT9611A is usually recommended to be utilized in performance oriented applications, such as high power density cpu vr or gpu vr. non-overlap control to prevent the overlap of the gate drives during the ugate pull low and the lgate pull high, the non-overlap circuit monitors the voltages at the phase node and high side gate drive (ugate-phase). when the pwm input signal goes low, ugate begins to pull low (after propagation delay). before lgate can pull high, the non-overlap protection circuit ensures that the monitored voltages have gone below 1.1v. once the monitored voltages fall below 1.1v, lgate begins to turn high. for short pulse condition, if the phase pin had not gone high after lgate pulls low, the lgate has to wait for 200ns before pull high. by waiting for the voltages of the phase pin and high side gate drive to fall below 1.1v, the non-overlap protection circuit ensures that ugate is low before lgate pulls high. also to prevent the overlap of the gate drives during lgate pull low and ugate pull high, the non-overlap circuit monitors the lgate voltage. when lgate go below 1.1v, ugate is allowed to go high. driving power mosfets the dc input impedance of the power mosfet is extremely high. when v gs1 or v gs2 is at 12v or 5v, the gate draws the current only for few nano-amperes. thus once the gate has been driven up to ? on ? level, the current could be negligible. however, the capacitance at the gate to source terminal should be considered. it requires relatively large currents to drive the gate up and down 12v (or 5v) rapidly. it is also required to switch drain current on and off with the required speed. the required gate drive currents are calculated as follows. application information the RT9611A/b is a high frequency, synchronous rectified, single phase dual mosfet driver containing richtek's advanced mosfet driver technologies. the RT9611A/b is designed to be able to adapt from normal mosfet driving applications to high performance cpu vr driving capabilities. the RT9611A/b can be utilized under both v cc = 5v or v cc = 12v applications which may happen in different fields of electronics application circuits. in the efficiency point of view, higher vcc equals higher driving voltage of ug/lg which may result in higher switching loss and lower conduction loss of power mosfets. the choice of v cc = 12v or v cc = 5v can be a tradeoff to optimize system efficiency. the RT9611A/b are designed to drive both high side and low side n-mosfet through external input pwm control signal. it has power on protection function which held ugate and lgate low before the vcc voltage rises to higher than rising threshold voltage. after the initialization, the pwm signal takes the control. the rising pwm signal first forces the lgate signal turns low then ugate signal is allowed to go high just after a non-overlapping time to avoid shoot through current. the falling of pwm signal first forces ugate to go low. when ugate and phase signal reach a predetermined low level, lgate signal is allowed to turn high. the pwm signal is acted as ? high ? if the signal is above the rising threshold and acted as ? low ? if the signal is below the falling threshold. any signal level enters and remains within the shutdown window is considered as ? tri- state ? the output drivers are disabled and both mosfet gates are pulled and held low. if left the pwm signal floating, the pin will be kept around 1.8v by the internal divider and provide the pwm controller with a recognizable level. od pin will also turn off both high/low side mosfets when tied to gnd. the RT9611A/b builds in an internal bootstrap power switch to replace external bootstrap diode, and this can facilitate pcb design and reduce total bom cost of the system. hence, no external bootstrap diode is required in real applications. the difference of the RT9611A and the rt9611b is the
RT9611A/b 10 ds9611a/b-03 june 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. l s 2 c gs1 c gd1 i gd1 i gs1 i g1 v out s 1 v in d 1 d 1 gnd g 1 d 2 c gs2 g 2 i g2 i gd2 i gs2 c gd2 d 2 figure1. equivalent circuit and associated waveforms in figure 1, the current i g1 and i g2 are required to move the gate up to 12v. the operation consists of charging c gd1 , c gd2 , c gs1 and c gs2 . c gs1 and c gs2 are the capacitors from gate to source of the high side and the low side power mosfets, respectively. in general data sheets, the c gs1 and c gs2 are referred as ? c iss ? which are the input capacitors. c gd1 and c gd2 are the capacitors from gate to drain of the high side and the low side power mosfets, respectively and referred to the data sheets as ? c rss ? the reverse transfer capacitance. for example, t r1 and t r2 are the rising time of the high side and the low side power mosfets respectively, the required current i gs1 and i gs2 , are shown as below : g1 gs1 gs1 gs1 r1 g2 gs1 gs2 gs1 r2 dv c x 12 ic dt t dv c x 12 ic dt t == == before driving the gate of the high side mosfet up to 12v (or 5v), the low side mosfet has to be off; and the high side mosfet is turned off before the low side is turned on. from figure 1, the body diode ? d 2 ? had been turned on before high side mosfets turned on. gd1 gd1 gd1 r1 dv 12 ic c dt t == (1) (2) (3) before the low side mosfet is turned on, the c gd2 have been charged to v in . thus, as c gd2 reverses its polarity and g 2 is charged up to 12v, the required current is : gd2 gd2 gd2 r2 dv vi 12 ic c dt t + == (4) it is helpful to calculate these currents in a typical case. assume a synchronous rectified buck converter, input voltage v in = 12v, v g1 = v g2 = 12v. the high side mosfet is phb83n03lt whose c iss = 1660pf, c rss = 380pf, and t r = 14ns. the low side mosfet is phb95n03lt whose c iss = 2200pf, c rss = 500pf and t r = 30ns, from the equation (1) and (2) we can obtain : -12 gs1 -9 -12 gs2 -9 1660 x 10 x 12 i 1.428 (a) 14 x 10 2200 x 10 x 12 i 0.88 (a) 30 x 10 == == (5) (6) from equation. (3) and (4) () -12 gd1 -9 -12 gd2 -9 380 x 10 x 12 i 0.326 (a) 14 x 10 500 x 10 x 12+12 i 0.4 (a) 30 x 10 == == (7) (8) the total current required from the gate driving source can be calculated as following equations : by a similar calculation, we can also get the sink current required from the turned off mosfet. select the bootstrap capacitor figure 2 shows part of the bootstrap circuit of the RT9611A/ b. the v cb (the voltage difference between boot and phase on RT9611A/b) provides a voltage to the gate of the high side power mosfet. this supply needs to be ensured that the mosfet can be driven. for this, the ( ) () =+= + = =+= += g1 gs1 gd1 g2 gs2 gd2 i i i 1.428 0.326 1.754 (a) (9) i i i 0.88 0.4 1.28 (a) (10) 12v t t v g2 v g1 v phase +12v
RT9611A/b 11 ds9611a/b-03 june 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. capacitance c b has to be selected properly. it is determined by following constraints. figure 2. part of bootstrap circuit of RT9611A/b in practice, a low value capacitor c b will lead to the over charging that could damage the ic. therefore, to minimize the risk of overcharging and to reduce the ripple on v cb , the bootstrap capacitor should not be smaller than 0.1 f, and the larger the better. in general design, using 1 f can provide better performance. at least one low esr capacitor should be used to provide good local de-coupling. it is recommended to adopt a ceramic or tantalum capacitor. power dissipation to prevent driving the ic beyond the maximum recommended operating junction temperature of 125 c, it is necessary to calculate the power dissipation appropriately. this dissipation is a function of switching frequency and total gate charge of the selected mosfet. figure 3 shows the power dissipation test circuit. c l and c u are the ugate and lgate load capacitors, respectively. the bootstrap capacitor value is 1 f. figure 3. test circuit figure 4 shows the power dissipation of the RT9611A/b as a function of frequency and load capacitance. the value of c u and c l are the same and the frequency is varied from 100khz to 1mhz. figure 4. power dissipation vs. frequency the operating junction temperature can be calculated from the power dissipation curves (figure 4). assume v cc = 12v, operating frequency is 200khz and c u = c l = 1nf which emulate the input capacitances of the high side and low side power mosfets. from figure 4, the power dissipation is 100m . thus, for example, with the sop-8 package thermal resistance ja is 120 c/ w. the operating junction temperature is calculated as : t j = (120 c/w x 100mw) + 25 c = 37 c (11) where the ambient temperature is 25 c. thermal considerations for recommended operating condition specifications of the RT9611A/b, the maximum junction temperature is 125 c and t a is the ambient temperature. the junction to ambient thermal resistance, ja , is layout dependent. for sop-8 packages, the thermal resistance, ja , is 120 c/ w on a standard jedec 51-7 four-layer thermal test board. for sop-8 (exposed pad) packages, the thermal resistance, ja , is 75 c/w on a standard jedec 51-7 four-layer thermal test board. for wdfn-8el 3x3 packages, the thermal resistance, ja , is 70 c/w on a standard jedec 51-7 four-layer thermal test board. the v in c b v cb + - boot v cc ugate phase lgate gnd c u 3nf vcc pwm gnd boot ugate phase lgate RT9611A/b 1f c l 3nf 20 2n7002 2n7002 12v 12v 1f pwm c boot 10 5v od power dissipation vs. frequency 0 100 200 300 400 500 600 700 800 900 1000 0 200 400 600 800 1000 frequency (khz) power dissipation (mw) c u = c l = 1nf c u = c l = 3nf c u = c l = 2nf
RT9611A/b 12 ds9611a/b-03 june 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 6. synchronous buck converter circuit when layout the pcb, it should be very careful. the power circuit section is the most critical one. if not configured properly, it will generate a large amount of emi. the junction of q1, q2, l2 should be very close. next, the trace from ugate, and lgate should also be short to decrease the noise of the driver output signals. phase signals from the junction of the power mosfet, carrying the large gate drive current pulses, should be as heavy as the gate drive trace. the bypass capacitor c4 should be connected to gnd directly. furthermore, the bootstrap capacitors (c b ) should always be placed as close to the pins of the ic as possible. maximum power dissipation at t a = 25 c can be calculated by the following formulas : p d(max) = (125 c ? 25 c) / (120 c/w) = 0.833w for sop-8 package p d(max) = (125 c ? 25 c) / (75 c/w) = 1.333w for sop-8 (exposed pad) package p d(max) = (125 c ? 25 c) / (70 c/w) = 1.429w for wdfn-8el 3x3 package the maximum power dissipation depends on the operating ambient temperature for fixed t j(max) and thermal resistance, ja . the derating curves in figure 5 allow the designer to see the effect of rising ambient temperature on the maximum power dissipation. layout consideration figure 6 shows the schematic circuit of a synchronous buck converter to implement the RT9611A/b. the converter operates from 5v to 12v of input voltage. figure 5. derating curve of maximum power dissipation boot ugate phase lgate vcc RT9611A/b 1 4 5 7 8 gnd 6 cb 12v l1 c3 v in v core c2 phb83n03lt phb95n03lt l2 q2 q1 c1 + + 12v pwm 2 pwm 3 5v od c4 r1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 0255075100125 ambient temperature (c) maximum power dissipation (w) 1 wdfn-8el 3x3 four-layer pcb sop-8 (exposed pad) sop-8
RT9611A/b 13 ds9611a/b-03 june 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. outline dimension a b j f h m c d i 8-lead sop plastic package dimensions in millimeters dimensions in inches symbol min max min max a 4.801 5.004 0.189 0.197 b 3.810 3.988 0.150 0.157 c 1.346 1.753 0.053 0.069 d 0.330 0.508 0.013 0.020 f 1.194 1.346 0.047 0.053 h 0.170 0.254 0.007 0.010 i 0.050 0.254 0.002 0.010 j 5.791 6.200 0.228 0.244 m 0.400 1.270 0.016 0.050
RT9611A/b 14 ds9611a/b-03 june 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. a b j f h m c d i y x exposed thermal pad (bottom of package) 8-lead sop (exposed pad) plastic package dimensions in millimeters dimensions in inches symbol min max min max a 4.801 5.004 0.189 0.197 b 3.810 4.000 0.150 0.157 c 1.346 1.753 0.053 0.069 d 0.330 0.510 0.013 0.020 f 1.194 1.346 0.047 0.053 h 0.170 0.254 0.007 0.010 i 0.000 0.152 0.000 0.006 j 5.791 6.200 0.228 0.244 m 0.406 1.270 0.016 0.050 x 2.000 2.300 0.079 0.091 option 1 y 2.000 2.300 0.079 0.091 x 2.100 2.500 0.083 0.098 option 2 y 3.000 3.500 0.118 0.138
RT9611A/b 15 ds9611a/b-03 june 2012 www.richtek.com richtek technology corporation 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 richtek products are sold by description only. richtek reserves the right to change the circuitry and/or specifications without notice at any time. customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a richtek product. information furnish ed by richtek is believed to be accurate and reliable. however, no responsibility is assumed by richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of r ichtek or its subsidiaries. dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 d 2.950 3.050 0.116 0.120 d2 2.200 2.700 0.087 0.106 e 2.950 3.050 0.116 0.120 e2 1.450 1.750 0.057 0.069 e 0.500 0.020 l 0.350 0.450 0.014 0.018 w-type 8el dfn 3x3 package (0.5mm lead pitch) 1 1 2 2 note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options d 1 e a3 a a1 d2 e2 l b e see detail a

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